View KAF-09000-ABA-DD-AE_8759696.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor components industries, llc, 2015 february, 2015 ? rev. 3 1 publication order number: kaf ? 09000/d kaf-09000 3056 (h) x 3056 (v) full frame ccd image sensor description combining high resolution with outstanding sensitivity, the kaf ? 09000 image sensor has been specifically designed to meet the needs of next ? generation low cost digital radiography and scientific imaging systems. the high sensitivity available from 12 ? micron square pixels combines with a low noise architecture to allow system designers to improve overall image quality, or to relax system tolerances to achieve lower cost. the excellent uniformity of the kaf ? 09000 image sensor improves overall image integrity by simplifying image corrections, while integrated anti ? blooming protection prevents image bleed from over ? exposure in bright areas of the image. to simplify device integration, the kaf ? 09000 image sensor uses the same pin ? out and package as the kaf ? 16801 image sensor. the sensor utilizes the truesense transparent gate electrode to improve sensitivity compared to the use of a standard front ? side illuminated polysilicon electrode. table 1. general specifications parameter typical value architecture full frame ccd [square pixels] total number of pixels 3103 (h) x 3086 (v) = 9.6 mp number of effective pixels 3085 (h) x 3085 (v) = 9.5 mp number of active pixels 3056 (h) x 3056 (v) = 9.3 mp pixel size 12 m (h) x 12 m (v) active image size 36.7 mm (h) x 36.7 mm (v) 51.9 mm diagonal, 645 1.3x optical format aspect ratio square horizontal outputs 1 saturation signal 110 ke ? output sensitivity 24 v/e ? quantum efficiency (550 nm) 64% responsivity (550 nm) 2595 ke/ j/cm 2 62.3 v/ j/cm 2 read noise (f = 3 mhz) 7 e ? dark signal (t = 25 c) 5 e/pix/sec dark current doubling temperature 7 c linear dynamic range (f = 4 mhz) 84 db blooming protection (4 ms exposure time) > 100 x saturation exposure maximum data rate 10 mhz package cerdip, (sidebrazed pins, cuw) cover glass ar coated 2 sides taped clear note: parameters above are specified at t = 25 c unless otherwise noted. www.onsemi.com figure 1. kaf ? 09000 ccd image sensor features ? truesense transparent gate electrode for high sensitivity ? large pixel size ? large image area ? high quantum efficiency ? low noise architecture ? broad dynamic range applications ? medical ? scientific see detailed ordering and shipping information on page 2 of this data sheet. ordering information
kaf ? 09000 www.onsemi.com 2 ordering information table 2. ordering information part number description marking code kaf ? 09000 ? aba ? dp ? ba monochrome, microlens, cerdip package, (sidebrazed, cuw), taped clear coverglass, standard grade kaf ? 09000 ? aba [serial number] kaf ? 09000 ? aba ? dp ? ae monochrome, microlens, cerdip package, (sidebrazed, cuw), taped clear coverglass, engineering sample kaf ? 09000 ? aba ? dd ? ba monochrome, microlens, cerdip package, (sidebrazed, cuw), ar coated 2 sides, standard grade kaf ? 09000 ? aba ? dd ? ae monochrome, microlens, cerdip package, (sidebrazed, cuw), ar coated 2 sides, engineering sample see the on semiconductor device nomenclature document (tnd310/d) for a full description of the naming convention used for image sensors. for reference documentation, including information on evaluation kits, please visit our web site at www.onsemi.com.
kaf ? 09000 www.onsemi.com 3 device description architecture figure 2. block diagram kaf ? 09000 3056 h x 3056 v 12 m x 12 m pixels 20 9 20 dark 9 18 4 1 3 1 test row v1 lod 20 413 2 vout sub og rg rd vdd vss 1 6 3056 91 h1 h2 v2 dark reference pixels the periphery of the device is surrounded with a border of light shielded pixels creating a dark region. within this dark region, there are 20 leading dark pixels on every line as well as 20 full dark lines at the start and 9 full dark lines at the end of every frame. under normal circumstances, these pixels do not respond to light and may be used as a dark reference. dummy pixels within each horizontal shift register there are 14 leading pixels and 3 trailing pixels. these are designated as dummy pixels and should not be used to determine a dark reference level. image acquisitio n an electronic representation of an image is formed when incident photons falling on the sensor plane create electron ? hole pairs within the device. these photon ? induced electrons are collected locally by the formation of potential wells at each pixel site. the number of electrons collected is linearly dependent on light level and exposure time and non ? linearly dependent on wavelength. when the pixel?s capacity is reached, excess electrons are discharged into the lateral overflow drain to prevent crosstalk or ?blooming?. during the integration period, the v1 and v2 register clocks are held at a constant (low) level. charge transport the integrated charge from each pixel is transported to the output using a two ? step process. each line (row) of charge is first transported from the vertical ccds to a horizontal ccd register using the v1 and v2 register clocks. the horizontal ccd is presented a new line on the falling edge of v2 while h1 is held high. the horizontal ccds then transport each line, pixel by pixel, to the output structure by alternately clocking the h1 and h2 pins in a complementary fashion.
kaf ? 09000 www.onsemi.com 4 horizontal register output structure figure 3. output architecture (left or right) floating diffusion hccd charge transfer source follower #1 source follower #2 source follower #3 rd rg og h1 h2 vdd vss vout the output consists of a floating diffusion capacitance connected to a three ? stage source follower. charge presented to the floating diffusion (fd) is converted into a voltage and is current amplified in order to drive off ? chip loads. the resulting voltage change seen at the output is linearly related to the amount of charge placed on the fd. once the signal has been sampled by the system electronics, the reset gate (rg) is clocked to remove the signal and fd is reset to the potential applied by reset drain (rd). increased signal at the floating diffusion reduces the voltage seen at the output pin. to activate the output structure, an off ? chip current source must be added to the vout pin of the device. see figure 4.
kaf ? 09000 www.onsemi.com 5 output load figure 4. recommended output structure load diagram 2n3904 or equiv. buffered video output iout = 5 ma vdd = +15 v 0.1 f vout 140 1 k note: component values may be revised based on operating conditions and other design considerations.
kaf ? 09000 www.onsemi.com 6 physical description pin description and device orientation figure 5. pinout diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 lod sub v2 v2 v1 v1 n/c n/c sub* sub* sub og vdd vout vss rd rg n/c v2 v2 v1 v1 sub n/c n/c n/c sub* n/c n/c n/c h2 h1 sub pixel (1,1) (3056,3056) n/c notes: 1. pins with the same name are to be tied together on the circuit board and have the same timing. 2. unlike the kaf ? 16801, pins 9, 10, and, 25 are internally connected to sub. they may be connected to sub on the printed circuit board or may be left floating. table 3. pin description pin name description 1 sub substrate 2 v2 vertical ccd clock ? phase 2 3 v2 vertical ccd clock ? phase 2 4 v1 vertical ccd clock ? phase 1 5 v1 vertical ccd clock ? phase 1 6 lod anti blooming drain 7 n/c no connection 8 n/c no connection 9 sub* no connection 10 sub* no connection 11 sub substrate 12 og output gate 13 vdd output amplifier supply 14 vout video output 15 vss output amplifier return 16 rd reset drain 17 rg reset gate 18 sub substrate 19 h1 horizontal phase 1 20 h2 horizontal phase 2 21 n/c no connection 22 n/c no connection 23 n/c no connection 24 n/c no connection 25 sub* no connection 26 n/c no connection 27 n/c no connection 28 n/c no connection 29 n/c no connection 30 sub substrate 31 v1 vertical ccd clock ? phase 1 32 v1 vertical ccd clock ? phase 1 33 v2 vertical ccd clock ? phase 2 34 v2 vertical ccd clock ? phase 2 *unlike the kaf ? 16801, pins 9, 10, and, 25 are internally connected to sub. they may be connected to sub on the printed circuit board or must be left floating.
kaf ? 09000 www.onsemi.com 7 imaging performance table 4. typical operational conditions description condition ? unless otherwise noted notes read out time treadout 2533 ms includes over clock pixels integration time (tint) variable horizontal clock frequency 4 mhz temperature 25 c room temperature mode integrate ? readout cycle operation nominal operating voltages and timing with min. vertical pulse width tvw = 20 s table 5. specifications description symbol min. nom. max. units notes verification plan saturation signal ne ? sat 95k 110k e ? die 11 quantum efficiency (550 nm) qe 64 % 1 design 12 photo response non ? linearity prnl 1 % 2 design 12 photo response non ? uniformity prnu 0.5 2.5 % 3 die 11 integration dark signal vdark, int 5 20 e/pix/sec 4 die 11 0.6 2.8 pa/cm 2 read out dark signal vdark, read 80 320 electrons 5 die 11 dark signal non ? uniformity dsnu 20 e/pix/sec 6 die 11 dark signal doubling temperature t 7 c design 12 read noise nr 7 14 e ? rms 7 design 12 linear dynamic range dr 84 db 8 design 12 blooming protection xab 100 x vsat 9 design 12 output amplifier sensitivity vout/ne ? 24 v/e design 12 dc offset, output amplifier vodc vrd ? 4 vrd ? 2.0 v 10 die 11 output amplifier bandwidth f ? 3db 88 mhz design 12 output impedance, amplifier rout 150 250 die 11 1. increasing output load currents to improve bandwidth will decrease these values. 2. worst case deviation from straight line fit, between 1% and 90% of vsat. 3. one sigma deviation of a 128 x 128 sample when ccd illuminated uniformly. 4. average of all pixels with no illumination at 25 c. 5. read out dark current depends on the read out time, primarily when the vertical ccd clocks are at their high levels. this is approximately 0.125 sec/image for nominal timing conditions, tvw = 20 s. the read out dark current will increase as tvw is increased. the readout dark current is also dependent on the operating temperature. the specification applies to 25 c. 6. average integration dark signal of any of 32 x 32 blocks within the sensor. (each block is 128 x 128 pixels) 7. output amplifier noise only. operating at pixel frequency up to 4 mhz, bandwidth <20 mhz, tint = 0, and no dark current shot noise. 8. 20log (vsat/vn) 9. xab is the number of times above the vsat illumination level that the sensor will bloom by spot size doubling. the spot size is 10% of the imager height. xab is measured at 4 ms. 10. video level offset with respect to ground. 11. a parameter that is measured on every sensor during production testing. 12. a parameter that is quantified during the design verification activity.
kaf ? 09000 www.onsemi.com 8 typical performance curves (qe) figure 6. typical spectral response 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 300 400 500 600 700 800 900 1000 1100 qe wavelength (nm) kaf ? 09000 spectral response figure 7. typical angle response 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 ? 40 ? 35 ? 30 ? 25 ? 20 ? 15 ? 10 ? 5 0 5 10152025303540 normalized angle response degrees horizontal vertical kaf ? 09000 angle response
kaf ? 09000 www.onsemi.com 9 figure 8. dark current kaf ? 09000 dark current 0.1 1 10 100 ? 10 ? 5 0 5 1015202530 temperature (c) electrons integration read out figure 9. noise floor kaf ? 09000 noise floor 0 5 10 15 20 ? 20 ? 10 0 10 20 30 40 temperature (c) noise (electrons) total noise (dark current, amplifier, system) ccd only (dark current, amplifier) system noise = 6.5 electrons (10mhz bandwidth)
kaf ? 09000 www.onsemi.com 10 figure 10. linearity kaf ? 09000 linearity 0.01 0.1 1 10 100 1000 10000 100000 1000000 1 10 100 1000 10000 integration time (arbitrary) signal measured percent deviation from fit fit
kaf ? 09000 www.onsemi.com 11 defect definitions operating conditions all cosmetic tests performed at approximately 25 c. table 6. specifications classification points clusters columns includes dead columns standard grade < 200 < 20 < 10 yes point defects dark: a pixel, which deviates by more than 6% from neighboring pixels when illuminated to 70% of saturation ? or ? bright: a pixel with dark current > 3,000 e/pixel/sec at 25 c cluster defect a grouping of not more than 10 adjacent point defects cluster defects are separated by no less than 4 good pixels in any direction column defect a grouping of more than 10 point defects along a single column ? or ? a column containing a pixel with dark current > 15,000 e/pixel/sec (bright column) ? or ? a column that does not meet the cte specification for all exposures less than the specified max sat. signal level and greater than 2 ke ? a pixel, which loses more than 250 e ? under 2 ke ? illumination (trap defect) column defects are separated by no less than 4 good columns. no multiple column defects (double or more) will be permitted. column and cluster defects are separated by at least 4 good columns in the x direction.
kaf ? 09000 www.onsemi.com 12 operation table 7. absolute maximum ratings description symbol minimum maximum units notes diode pin voltages v diode ?0.5 +20 v 1, 2 adjacent gate pin voltages v gate1 ? 18 +18 v 1, 3 isolated gate pin voltages v 1 ? 2 ? 0.5 +20 v 4 output bias current i out ? 30 ma 5 lod diode voltage v lod ? 0.5 ? 13.0 v 6 operating temperature t op ? 60 60 c 7 stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. referenced to pin sub 2. includes pins: rd, vdd, vss, vout. 3. includes pins: v1, v2, h1, h2, vog. 4. includes pins: rg. 5. avoid shorting output pins to ground or any low impedance source during operation. amplifier bandwidth increases at higher cu rrents and lower load capacitance at the expense of reduced gain (sensitivity). operation at these values will reduce mttf. 6. v1, h1, v2, h2, h1l, vog, and rd are tied to 0 v. 7. noise performance will degrade at higher temperatures due to the temperature dependence of the dark current. 8. absolute maximum rating is defined as a level or condition that should not be exceeded at any time. if the level or condition is exceeded, the device will be degraded and may be damaged. power ? up sequence the sequence chosen to perform an initial power ? up is not critical for device reliability. a coordinated sequence may minimize noise and the following sequence is recommended: 1. connect the ground pins (sub). 2. supply the appropriate biases and clocks to the remaining pins. table 8. dc bias operating conditions description symbol minimum nominal maximum units maximum dc current (ma) notes reset drain v rd 12.8 13 13.2 v i rd = 0.01 output amplifier supply v ss 1.8 2.0 2.2 v i ss = 3.0 output amplifier return v dd 14.8 15.0 17.0 v i out + i ss substrate v sub 0 v 0.01 output gate v og 0 1 2 v 0.01 lateral overflow drain v lod 7.8 8.0 9.0 v 0.01 video output current i out ? 3 ? 5 ? 7 ma 1 1. an output load sink must be applied to vout to activate output amplifier ? see figure 4. ac operating conditions table 9. clock levels description symbol level minimum nominal maximum units notes v1 low level v1l low ? 9.5 ? 9.0 ? 8.5 v 1 v1 high level v1h high 2.3 2.5 2.7 v 1 v2 low level v2l low ? 9.5 ? 9.0 ? 8.5 v 1 v2 high level v2h high 2.3 2.5 2.7 v 1 h1 low level h1l low ? 2.5 ? 2 ? 1.7 v 1 h1 high level h1h high 7.5 8 8.2 v 1 1. all pins draw less than 10 a dc current. capacitance values relative to sub (substrate).
kaf ? 09000 www.onsemi.com 13 table 9. clock levels description notes units maximum nominal minimum level symbol h2 low level h2l low ? 2.5 ? 2 ? 1.7 v 1 h2 high level h2h high 7.5 8 8.2 v 1 rg low level rgl low 5.3 5.5 5.7 v 1 rg high level rgh high 11.2 11 10.8 v 1 1. all pins draw less than 10 a dc current. capacitance values relative to sub (substrate). capacitance equivalent circuit figure 11. equivalent circuit model lod v1 v2 h2 h1 c lod c lod_v1 c lod_v2 c v1_v2 c v1 c v2 c vh c h1 c h2 c h1_h2 og c og c h1_og rg c rg table 10. description label value unit lod ? sub capacitance c lod 6.5 nf lod ? v1 capacitance c lod_v1 36 nf lod ? v2 capacitance c lod_v2 36 nf v1 ? v2 capacitance c v1_v2 80 nf v1 ? sub capacitance c v1_sub 250 nf v2 ? sub capacitance c v2_sub 250 nf v2 ? h1 capacitance c vh 36 pf h1 ? h2 capacitance c h1_h2 75 pf h1 ? sub capacitance c h1_sub 500 pf h2 ? sub capacitance c h2_sub 300 pf og ? sub capacitance c og_sub 5 pf rg ? sub capacitance c rg_sub 13 pf
kaf ? 09000 www.onsemi.com 14 timing table 11. requirements and characteristics description symbol minimum nominal maximum units notes h1, h2 clock frequency f h 4 10 mhz 1 h1, h2 rise, fall times t h1r , t h1f 5 % 3 v1, v2 rise, fall times t v1r , t v1f 5 % 3 v1 ? v2 cross ? over v vcr ? 1 0 1 v h1 ? h2 cross ? over v hcr 2 3 5 v h1, h2 setup time t hs 5 10 s rg clock pulse width t rgw 5 10 ns 4 v1, v2 clock pulse width t vw 20 20 s pixel period (1 count) t e 250 ns 2 readout time t readout 2,533 ms 7 integration time t int 5 line time t line 0.821 ms 6 1. 50% duty cycle values. 2. cte will degrade above the maximum frequency. 3. relative to the pulse width (based on 50% of high/low levels). 4. rg should be clocked continuously. 5. integration time is user specified. 6. (3103 * t e ) + t hs + (2 * t vw ) = 0.821 msec 7. t readout = t line * 3086 lines edge alignment figure 12. timing edge alignment v hcr h1 v1 v2 v vcr v1,v2
kaf ? 09000 www.onsemi.com 15 frame timing figure 13. frame timing line 1 2 3 3085 3086 1 frame = 3086lines t readout t int v2 v1 h2 h1 frame timing detail figure 14. frame timing detail v1 v2 t v1f 90% 10% t v1r t v2r 90% 10% t v2f t vw line timing figure 15. line timing t hs 3103 t e t line v1 v2 h1 h2 rg t v t v line content 1 ? 11 12 ? 15 16 ? 35 36 ? 3091 ?? ?? ?? ?? ?? ? ? ? ?? ?? ? ? ? ? 3100 3101 ? 3103
kaf ? 09000 www.onsemi.com 16 pixel timing figure 16. pixel timing pixel timing detail figure 17. pixel timing detail rg lo h1, h1 low h2 lo 90 % 50 % h1 amp , h 2 amp t e t h12 r t h12 f 10 % t rg r r 10 % t rgf rg amp t rg w 2 90 %
kaf ? 09000 www.onsemi.com 17 example waveforms figure 18. horizontal clocks figure 19. video waveform note: the upper waveform was taken at the ccd output and the lower waveform was taken at the analog to digital converter, and is bandwidth limited.
kaf ? 09000 www.onsemi.com 18 figure 20. video waveform and clamp clock figure 21. video waveform and sample clock
kaf ? 09000 www.onsemi.com 19 storage and handling table 12. storage conditions description symbol minimum maximum units notes storage temperature t st ? 20 70 c 1 1. long term storage toward the maximum temperature will accelerate color filter degradation. for information on esd and cover glass care and cleanliness, please download the image sensor handling and best practices application note (an52561/d) from www.onsemi.com . for information on soldering recommendations, please download the soldering and mounting techniques reference manual (solderrm/d) from www.onsemi.com . for quality and reliability information, please download the quality & reliability handbook (hbd851/d) from www.onsemi.com . for information on device numbering and ordering codes, please download the device nomenclature technical note (tnd310/d) from www.onsemi.com . for information on standard terms and conditions of sale, please download terms and conditions from www.onsemi.com .
kaf ? 09000 www.onsemi.com 20 mechanical information completed assembly figure 22. completed assembly (1 of 1)
kaf ? 09000 www.onsemi.com 21 cover glass specification mar glass for sealed cover 1. scratch and dig: 10 micron max 2. substrate material schott d263t eco or equivalent 3. multilayer anti ? reflective coating table 13. wavelength total reflectance 420 ? 450 2% 450 ? 630 1% 630 ? 680 2% on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warrant y, representation or guarantee regarding the suitability of it s products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 kaf ? 09000/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

▲Up To Search▲

Price & Availability of KAF-09000-ABA-DD-AE

	To Download KAF-09000-ABA-DD-AE Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .